LUT-SR RNG For Bit By Bit Operations Using Pipelining Architecture

Kuma Satyanarayana, Gagandeep Taddi

Abstract


Most of the RNG mathematicians analyse on the basis of software terms, which can be proved from their designed algorithms. They assume that the execution in the existing environment is word-based and sequential. FPGAs are based on bit-by-bit operations and are rigidly parallel. Therefore, mapping the algorithms from a software based environment to hardware based environment leads to inefficient conditions. The wastefulness may bring about a few issues including untrackable rate of the generator, lower clock rates, fractional use of assets, lesser utilization of RAMS, non-uniform word lengths.


References


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